The generation of complex multiple timing cycles for digital logic systems commonly requires extensive complex logic circuitry. The verification of the operation of the timing circuitry in the past has imposed additional complexity on the design requirements of the system and has not provided a high level of confidence verification.
In digital logic systems, programmable read-only memory (PROM) is commonly used to store programs and data which are normally accessed by the host computer during operation. Additional PROM is often utilized for the storage and generation of the timing signals for the system. This PROM is not normally accessible by the host computer.
Also included in the system is a buffer and logic circuit. This is a group of buffers, combinational logic and sequential logic circuits which receive timing inputs from the PROM and timing and control inputs from other sources in the system. The buffer and logic circuit acts on these various inputs to produce a selected one of the several possible complex timing cycles.
This system consisting of the PROM and the buffer and logic circuit, has two modes of operation, a Normal mode for normal system operation and a Verify mode for timing cycle verification. In the Normal mode, a free running clock is coupled to an address counter, which successively selects a row in the PROM, which upon selection outputs the stored information in that row to the buffer and logic section. In this mode the address counter operates in a cyclic manner on a continuous basis, and the PROM is read out from the starting to the ending address of the PROM section which is employed for the particular timing mode that is selected. In the Verify mode, the free running clock is disconnected and replaced with a host computer controlled clock which is stepped pulse by pulse so that the address counter steps through the rows of the PROM at a rate controlled directly by the host computer.
Verification of programs stored in programmable read-only memory (PROM) is generally achieved through the use of diagnostic software routines which utilize a checksum operation. The present invention utilizes a PROM which has several sections, each of which stores timing information for a different selectable mode. In normal operation this timing information is only used to generate complex timing cycles, and it is not required to be accessible to the host computer. In order to verify correct operation of the timing circuits, the host computer, or an independent control section switches the timing circuit at a rate which allows the adder to provide a checksum for each row of the PROM, which is added to the checksum provided by all of the preceding rows. The digital checksum that is achieved is compared with a stored checksum which is known to be correct for the selected complex timing cycle. The present invention is thereby capable of providing diagnostic verification with a high level of confidence, for several different complex timing cycles that may be generated for timing the data processing system. For example, the timing generation may be used with a mass memory controller to ensure that the required timing cycles occur in the correct sequences and with the correct intervals.